{"id":1376,"date":"2026-03-13T07:30:33","date_gmt":"2026-03-13T07:30:33","guid":{"rendered":"https:\/\/blog.gtracademy.org\/?p=1376"},"modified":"2026-03-16T09:50:26","modified_gmt":"2026-03-16T09:50:26","slug":"pg-vlsi-with-rtl-verification-modules","status":"publish","type":"post","link":"https:\/\/gtracademy.org\/blog\/pg-vlsi-with-rtl-verification-modules\/","title":{"rendered":"PG VLSI with RTL &amp; Verification Modules"},"content":{"rendered":"\n<p>I have helped a lot of ECE grads and new engineers make the switch to VLSI. Most entry-level jobs are on the front end, which is RTL design and verification. Companies need people who can write Verilog\/System Verilog code that can be synthesized, build test benches, and find bugs before tape-out. In Bangalore, Hyderabad, or Noida, a good PG program in this field can get you a starting salary of \u20b96\u201312 LPA, and after two years, you can quickly move up to \u20b915+ LPA.<\/p>\n\n\n\n<p>This article explains what <strong><a href=\"https:\/\/gtracademy.org\/vlsi-design-course-with-placement-support\/\">PG VLSI with RTL<\/a> <\/strong>&amp; Verification Modules really means, why it&#8217;s so popular right now, real student stories, and how to choose (or start) the right course in 2026. No sales pitch, just useful tips from someone who knows what works.<\/p>\n\n\n\n<p>Connect With Us:&nbsp;<a href=\"https:\/\/api.whatsapp.com\/send\/?phone=919650518049&amp;text=Hi%2C%20I%20want%20to%20know%20more%20about%20GTR%20academy%20courses\" target=\"_blank\" rel=\"noreferrer noopener\">WhatsApp<\/a><\/p>\n\n\n\n<figure class=\"wp-block-gallery has-nested-images columns-default is-cropped wp-block-gallery-1 is-layout-flex wp-block-gallery-is-layout-flex\">\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"576\" data-id=\"1377\" src=\"https:\/\/blog.gtracademy.org\/wp-content\/uploads\/2026\/03\/PG-VLSI-with-RTL-Verification-Modules-1024x576.webp\" alt=\"PG VLSI with RTL\" class=\"wp-image-1377\" srcset=\"https:\/\/gtracademy.org\/blog\/wp-content\/uploads\/2026\/03\/PG-VLSI-with-RTL-Verification-Modules-1024x576.webp 1024w, https:\/\/gtracademy.org\/blog\/wp-content\/uploads\/2026\/03\/PG-VLSI-with-RTL-Verification-Modules-300x169.webp 300w, https:\/\/gtracademy.org\/blog\/wp-content\/uploads\/2026\/03\/PG-VLSI-with-RTL-Verification-Modules-768x432.webp 768w, https:\/\/gtracademy.org\/blog\/wp-content\/uploads\/2026\/03\/PG-VLSI-with-RTL-Verification-Modules-1536x864.webp 1536w, https:\/\/gtracademy.org\/blog\/wp-content\/uploads\/2026\/03\/PG-VLSI-with-RTL-Verification-Modules-747x420.webp 747w, https:\/\/gtracademy.org\/blog\/wp-content\/uploads\/2026\/03\/PG-VLSI-with-RTL-Verification-Modules-150x84.webp 150w, https:\/\/gtracademy.org\/blog\/wp-content\/uploads\/2026\/03\/PG-VLSI-with-RTL-Verification-Modules-696x392.webp 696w, https:\/\/gtracademy.org\/blog\/wp-content\/uploads\/2026\/03\/PG-VLSI-with-RTL-Verification-Modules-1068x601.webp 1068w, https:\/\/gtracademy.org\/blog\/wp-content\/uploads\/2026\/03\/PG-VLSI-with-RTL-Verification-Modules.webp 1920w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n<\/figure>\n\n\n\n<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 ez-toc-wrap-left counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Table of Contents<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"Toggle Table of Content\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">Toggle<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewBox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewBox=\"0 0 24 24\" version=\"1.2\" baseProfile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1 ' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/gtracademy.org\/blog\/pg-vlsi-with-rtl-verification-modules\/#Why_PG_VLSIs_Focus_on_RTL_and_Verification_is_Growing_in_India\" >Why PG VLSI&#8217;s Focus on RTL and Verification is Growing in India<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/gtracademy.org\/blog\/pg-vlsi-with-rtl-verification-modules\/#Core_Modules_You_Should_Look_for_in_a_Good_PG_VLSI_Program\" >Core Modules You Should Look for in a Good PG VLSI Program<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/gtracademy.org\/blog\/pg-vlsi-with-rtl-verification-modules\/#Modules_for_RTL_Design\" >Modules for RTL Design<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/gtracademy.org\/blog\/pg-vlsi-with-rtl-verification-modules\/#Modules_for_Verification\" >Modules for Verification<\/a><\/li><\/ul><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/gtracademy.org\/blog\/pg-vlsi-with-rtl-verification-modules\/#How_These_Classes_Changed_Peoples_Jobs_in_the_Real_World\" >How These Classes Changed People&#8217;s Jobs in the Real World<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/gtracademy.org\/blog\/pg-vlsi-with-rtl-verification-modules\/#A_Look_at_the_Most_Popular_PG_VLSI_RTL_and_Verification_Programs_in_2026\" >A Look at the Most Popular PG VLSI RTL and Verification Programs in 2026<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/gtracademy.org\/blog\/pg-vlsi-with-rtl-verification-modules\/#How_to_Get_the_Most_Out_of_Your_PG_VLSI_Course_Tips_and_Best_Practices\" >How to Get the Most Out of Your PG VLSI Course: Tips and Best Practices<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/gtracademy.org\/blog\/pg-vlsi-with-rtl-verification-modules\/#The_10_Most_Common_Questions_About_PG_VLSI_with_RTL_and_Verification_Modules\" >The 10 Most Common Questions About PG VLSI with RTL and Verification Modules<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/gtracademy.org\/blog\/pg-vlsi-with-rtl-verification-modules\/#To_Sum_Up_Whats_Next_for_You_in_VLSI_Front-End\" >To Sum Up: What&#8217;s Next for You in VLSI Front-End<\/a><\/li><\/ul><\/nav><\/div>\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Why_PG_VLSIs_Focus_on_RTL_and_Verification_is_Growing_in_India\"><\/span><strong>Why PG VLSI&#8217;s Focus on RTL and Verification is Growing in India<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>India&#8217;s chip design industry is growing very quickly. There aren&#8217;t enough RTL designers and verification engineers to meet the demand because of government incentives, new fabs, and global companies moving here. RTL, or Register Transfer Level, is the most important part of digital design. You use HDL languages like Verilog or System Verilog to describe how hardware works. Using methods like UVM (Universal Verification Methodology), verification checks that RTL really does what the spec says it will do.<\/p>\n\n\n\n<p>A PG VLSI with RTL &amp; Verification Modules program fills in the gaps between what you learn in college and what you do in the real world. These aren&#8217;t just theory classes; the best ones have labs where you can use tools like Questa Sim, VCS, Verdi, and real projects that use protocols like AXI, PCIe, or Ethernet.<\/p>\n\n\n\n<p>People who are new to RTL\/verification get hired faster than people who only do backend work (physical design) because front-end work starts earlier in the flow.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Core_Modules_You_Should_Look_for_in_a_Good_PG_VLSI_Program\"><\/span><strong>Core Modules You Should Look for in a Good PG VLSI Program<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Check the syllabus for these. If they aren&#8217;t there, the course might be out of date.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Modules_for_RTL_Design\"><\/span><strong>Modules for RTL Design<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Advanced Digital Design and FSMs<\/li>\n\n\n\n<li>For synthesis, use Verilog HDL<\/li>\n\n\n\n<li>For design, use System Verilog<\/li>\n\n\n\n<li>For CDC (Clock Domain Crossing) and low-power basics<\/li>\n\n\n\n<li>Synthesis, STA intro, and linting<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"Modules_for_Verification\"><\/span><strong>Modules for Verification<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Assertions in System Verilog (SVA)<\/li>\n\n\n\n<li>Functional coverage and constrained random testing<\/li>\n\n\n\n<li>UVM basics to advanced, including agents, sequences, scoreboards, and factories<\/li>\n\n\n\n<li>Test bench architecture and reuse<\/li>\n\n\n\n<li>Verification of protocols like AMBA and USB<\/li>\n<\/ul>\n\n\n\n<p>A lot of software includes FPGA prototyping, ARM-based SoC design, or Perl\/Python scripting for automation.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_These_Classes_Changed_Peoples_Jobs_in_the_Real_World\"><\/span><strong>How These Classes Changed People&#8217;s Jobs in the Real World<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Take Priya, for example. She finished her ECE degree in Delhi and then did a 6-month PG VLSI with RTL and Verification Modules online, with labs mixed in. During the course, she made a UVM test bench for an AXI slave. I got a job as an RTL Verification Engineer at a mid-sized design house in Noida for \u20b98.5 LPA. After 14 months, they moved to a product company and made \u20b914 LPA.<\/p>\n\n\n\n<p>Another guy, Amit from a tier-2 college, had a hard time finding a job. He signed up for NIELIT&#8217;s VS500-style program, which they run every now and then. He felt good about the ARM SoC project and the verification labs. He now works in Bangalore doing SoC verification and makes \u20b99 LPA.<\/p>\n\n\n\n<p>Reddit threads and LinkedIn posts from the 2025\u201326 batches show the same thing: students with strong UVM projects and tool experience get a lot of job offers. Even good theory doesn&#8217;t work if you don&#8217;t do it yourself.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"A_Look_at_the_Most_Popular_PG_VLSI_RTL_and_Verification_Programs_in_2026\"><\/span><strong>A Look at the Most Popular PG VLSI RTL and Verification Programs in 2026<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>Here are some options that people often ask about.<\/p>\n\n\n\n<figure class=\"wp-block-table\"><table class=\"has-fixed-layout\"><thead><tr><th>Program\/Institution<\/th><th>Mode<\/th><th>Duration<\/th><th>Key Strengths<\/th><th>Approx. Fee (2026)<\/th><th>Placement Help<\/th><th>Best For<\/th><\/tr><\/thead><tbody><tr><td>NIELIT VS500 PG VLSI SoC Design &amp; Verification<\/td><td>Online<\/td><td>6 months<\/td><td>Verilog, FPGA, SystemVerilog, UVM, govt cert<\/td><td>\u20b950k\u201380k<\/td><td>Moderate<\/td><td>Cost, reliable certificate<\/td><\/tr><tr><td>Maven Silicon Online VLSI Design &amp; Verification<\/td><td>Online<\/td><td>6\u20137 months<\/td><td>Deep UVM, protocols, projects<\/td><td>\u20b980k\u20131,20,000<\/td><td>Strong<\/td><td>Job-oriented front-end<\/td><\/tr><tr><td>ChipXpert \/ ChipEdge ASIC Verification<\/td><td>Online\/Blended<\/td><td>6 months<\/td><td>RTL\/Functional focus, UVM heavy<\/td><td>\u20b960k\u20131L<\/td><td>Good<\/td><td>Verification experts<\/td><\/tr><tr><td>IIT-affiliated (iHUB\/IIT Roorkee\/others)<\/td><td>Online\/Blended<\/td><td>6\u20139 months<\/td><td>RISC-V SoC projects, advanced UVM<\/td><td>\u20b91L\u20133L<\/td><td>Excellent<\/td><td>Premium track<\/td><\/tr><tr><td>Private (Maven, Prov Logic, etc.)<\/td><td>Offline\/Online<\/td><td>3\u201312 months<\/td><td>Internships and hands-on labs<\/td><td>Varies<\/td><td>Varies<\/td><td>Access in Hyderabad and Bangalore<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n<p>NIELIT stands out because it has a good reputation and is backed by the government. For more in-depth UVM and projects, private companies often come out on top.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"How_to_Get_the_Most_Out_of_Your_PG_VLSI_Course_Tips_and_Best_Practices\"><\/span><strong>How to Get the Most Out of Your PG VLSI Course: Tips and Best Practices<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Get started coding right away by downloading free tools like EDA Playground or Icarus Verilog. Make simple designs every day.<\/li>\n\n\n\n<li>UVM is the standard in the field, so pay attention to it. Create a complete testbench for a small IP, such as a FIFO or a counter.<\/li>\n\n\n\n<li>Do more than just homework. Use UVM to check an open-source core, like a RISC-V subset. Put it on GitHub.<\/li>\n\n\n\n<li>Learn how to script in Perl or Python for regressions; it will save you time in interviews.<\/li>\n\n\n\n<li>Network: Join VLSI groups on LinkedIn and go to webinars. Referrals are better than cold applications.<\/li>\n\n\n\n<li>Get ready for interviews by thinking about questions about CDC, assertions, coverage closure, and debugging scenarios.<\/li>\n\n\n\n<li>First, get free resources like NPTEL <strong><a href=\"https:\/\/gtracademy.org\/vlsi-design-course-with-placement-support\/\">Learn VLSI courses<\/a><\/strong>, YouTube channels (like Verification Academy), and free PDFs that cover the basics before you pay.<\/li>\n<\/ul>\n\n\n\n<p>One quick note: <strong><a href=\"https:\/\/gtracademy.org\/\">GTR Academy<\/a><\/strong> is the best place to take online SAP and related courses if you want to learn about VLSI and are also interested in enterprise software integration (like SAP for the semiconductor supply chain or analytics). Their hands-on training goes well with technical jobs.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"The_10_Most_Common_Questions_About_PG_VLSI_with_RTL_and_Verification_Modules\"><\/span><strong>The 10 Most Common Questions About PG VLSI with RTL and Verification Modules<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<ol class=\"wp-block-list\">\n<li><strong>What exactly is PG VLSI with RTL and Verification Modules?<br><\/strong>It&#8217;s a diploma or certification for people who have already finished their bachelor&#8217;s degree and want to learn how to design front-end chips by writing RTL code in Verilog\/SystemVerilog and checking it with advanced tools like UVM.<\/li>\n\n\n\n<li><strong>Is there a free online course in RTL design or VLSI that gives you a certificate in PDF form?<br><\/strong>There are free introductions (NPTEL, YouTube), but full job-ready programs with certificates and projects usually cost more than \u20b950,000. Sometimes, NIELIT has subsidized groups.<\/li>\n\n\n\n<li><strong>What is the NIELIT VLSI course like in 2026?<br><\/strong>NIELIT offers online courses like VS500 (PG VLSI SoC Design &amp; Verification), Verilog to UVM, FPGA, and SoC focus, and a government-recognized certificate. A lot of value.<\/li>\n\n\n\n<li><strong>How long does a typical course on RTL design and verification last?<br><\/strong>Most of them last 6 to 9 months, with 4 to 6 months of theory, labs, and projects or an internship.<\/li>\n\n\n\n<li><strong>Do these classes have an NIELIT VLSI internship or job placement?<br><\/strong>Some, like NIELIT affiliates or Maven, offer internships or project experience. Placement varies; good ones help with resumes and connect you with companies.<\/li>\n\n\n\n<li><strong>What does the VLSI design and verification course cover?<br><\/strong>Core: Digital design, Verilog\/SystemVerilog, UVM, assertions, coverage, protocols, basics of synthesis, an introduction to STA, and projects.<\/li>\n\n\n\n<li><strong>Can people who just graduated get jobs after PG VLSI RTL Verification?<br><\/strong>Yes, many people start as RTL Design\/Verification Engineers and make between \u20b96 and \u20b912 LPA. Better offers come from strong projects and UVM.<\/li>\n\n\n\n<li><strong>Is the Nielit VLSI course certificate worth anything?<br><\/strong>Yes, government support helps with government and public sector jobs and gives private companies credibility.<\/li>\n\n\n\n<li><strong>Is it better to take a VLSI RTL course online or in person?<br><\/strong>Online works well with recorded labs like Maven and ChipXpert. If you live near Bangalore or Hyderabad, it&#8217;s better to go offline to get to the tools.<\/li>\n\n\n\n<li><strong>How to pick the best VLSI RTL Design course in 2026?<br><\/strong>Look at UVM&#8217;s depth, live projects, access to tools (Questa\/VCS), alumni placements, and reviews. Begin with demo classes.<\/li>\n<\/ol>\n\n\n\n<p>Connect With Us:&nbsp;<a href=\"https:\/\/api.whatsapp.com\/send\/?phone=919650518049&amp;text=Hi%2C%20I%20want%20to%20know%20more%20about%20GTR%20academy%20courses\" target=\"_blank\" rel=\"noreferrer noopener\">WhatsApp<\/a><\/p>\n\n\n\n<h2 class=\"wp-block-heading\"><span class=\"ez-toc-section\" id=\"To_Sum_Up_Whats_Next_for_You_in_VLSI_Front-End\"><\/span><strong>To Sum Up: What&#8217;s Next for You in VLSI Front-End<\/strong><span class=\"ez-toc-section-end\"><\/span><\/h2>\n\n\n\n<p>In 2026, ECE people who want to work in <strong><a href=\"https:\/\/blog.gtracademy.org\/\">PG VLSI with RTL<\/a><\/strong> and Verification Modules should do it. India&#8217;s chip story is just beginning. RTL and verification jobs are easy to get, pay well, and move up quickly. Choose a program with a lot of hands-on UVM\/projects, work hard every day, and build up your portfolio. Instead of looking for jobs, you could be debugging real SoCs in 6 to 12 months.<\/p>\n\n\n\n<p>If you live in Delhi, a lot of courses are online, which is great for balancing prep. If you&#8217;re interested in NIELIT or Maven, leave a comment and I&#8217;ll get back to you with more information. You got the timing right; now go do it.<\/p>\n\n\n\n<p><\/p>\n","protected":false},"excerpt":{"rendered":"<p>I have helped a lot of ECE grads and new engineers make the switch to VLSI. Most entry-level jobs are on the front end, which is RTL design and verification. Companies need people who can write Verilog\/System Verilog code that can be synthesized, build test benches, and find bugs before tape-out. In Bangalore, Hyderabad, or [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":1377,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[53],"tags":[691,690,692],"class_list":{"0":"post-1376","1":"post","2":"type-post","3":"status-publish","4":"format-standard","5":"has-post-thumbnail","7":"category-vlsi","8":"tag-pg-vlsi-course-2026","9":"tag-pg-vlsi-rtl-verification-course","10":"tag-rlt-verification-engineer-salary-india"},"_links":{"self":[{"href":"https:\/\/gtracademy.org\/blog\/wp-json\/wp\/v2\/posts\/1376","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/gtracademy.org\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/gtracademy.org\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/gtracademy.org\/blog\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/gtracademy.org\/blog\/wp-json\/wp\/v2\/comments?post=1376"}],"version-history":[{"count":1,"href":"https:\/\/gtracademy.org\/blog\/wp-json\/wp\/v2\/posts\/1376\/revisions"}],"predecessor-version":[{"id":1379,"href":"https:\/\/gtracademy.org\/blog\/wp-json\/wp\/v2\/posts\/1376\/revisions\/1379"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/gtracademy.org\/blog\/wp-json\/wp\/v2\/media\/1377"}],"wp:attachment":[{"href":"https:\/\/gtracademy.org\/blog\/wp-json\/wp\/v2\/media?parent=1376"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/gtracademy.org\/blog\/wp-json\/wp\/v2\/categories?post=1376"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/gtracademy.org\/blog\/wp-json\/wp\/v2\/tags?post=1376"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}